Embodiments relate to test map classification methods and fabrication process condition setting methods using the same.
With advancements in semiconductor technologies, technology for device design, technology for a unit process, and technology for process management are becoming more important. In particular, error minimization through innovation in process technology is essential to improving semiconductor manufacturing yield. Accordingly, there is a requirement for a series of steps of detecting defects occurring at various positions of a wafer during development of optimized process technology and a manufacturing process and analyzing the detected defects to be used as data for optimized process setting of a manufacturing apparatus.
In general, a semiconductor manufacturing process includes a pre-process, a post-process, and a test process. The pre-process is also referred to as a fabrication process in which integrated circuit patterns are formed on a semiconductor wafer made of single-crystalline silicon. The post-process is also referred to as an assembly process in which an integrated circuit package is formed by separating individual chips from the semiconductor wafer, connecting conductive leads or balls to the chips to be electrically connected to an external device, and molding the chips with a resin such as an epoxy resin to be protected from an external environment.
The test process is performed to test whether the integrated circuit package is normally operable and sort the chips into non-defective chips and defective chips. Before the assembly process is performed, an electrical die sorting (EDS) process is performed to inspect electrical characteristics of the respective chips constituting the semiconductor wafer. In the EDS process, after repairable chips and non-repairable chips are identified among the respective chips, the repairable chips are repaired while the non-repairable chips are eliminated. Therefore, the EDS process serves to reduce time and costs required for the assembly process and the test process.
When the fabrication process (pre-process) is completed, defect analysis processes are performed by a predetermined inspection apparatus to detect defects on the entire surface of the semiconductor wafer and sort the detected defects.